View M25P80_4195787.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M25P80
8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface
Features

SPI bus compatible serial interface 75 MHz Clock rate (maximum) 2.7 V to 3.6 V single supply voltage 8 Mbit of Flash memory Page Program (up to 256 bytes) in 0.64 ms (typical) Sector Erase (512 Kbit) in 0.6 s (typical) Bulk Erase (8 Mbit) in 8 s (typical) Hardware Write protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2) Deep Power-down mode 1 A (typical) Electronic signatures - JEDEC Standard two-byte signature (2014h) - Unique ID code (UID) +16 bytes of CFI data - RES instruction one-byte signature (13h) for backward compatibility More than 100 000 Program/Erase cycles per sector More than 20 years' data retention Packages - ECOPACK(R) (RoHS compliant) SO8W (MW) 208 mils width VFQFPN8 (MP) 6 x 5 mm (MLP8)

SO8N (MN) 150 mils width
December 2007
Rev 16
1/52
www.numonyx.com 1
Contents
M25P80
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . 12 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 6.2 6.3 6.4 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 6.4.2 6.4.3 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/52
M25P80 6.4.4
Contents SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 27 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Release from Deep Power-down and Read Electronic Signature (RES) . 33
7 8 9 10 11 12 13
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/52
List of tables
M25P80
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AC characteristics (75 MHz operation, Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AC characteristics (25 MHz operation, Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4/52
M25P80
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VFQFPN and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21 Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23 Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26 Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Write Protect setup and hold timing during WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . 44 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . 47 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 48
5/52
Description
M25P80
1
Description
The M25P80 is an 8 Mbit (1 Mbit x 8) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1,048,576 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. In order to meet environmental requirements, Numonyx offers the M25P80 in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. Figure 1. Logic diagram
VCC
D C S W HOLD M25P80
Q
VSS
AI04964
Table 1.
Signal names
Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Input Input Output Input Input Input Direction
Signal name C D Q S W HOLD VCC VSS
6/52
M25P80 Figure 2. VFQFPN and SO8 connections
M25P80 S Q W VSS 1 2 3 4 8 7 6 5
AI04965B
Description
VCC HOLD C D
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1.
7/52
Signal description
M25P80
2
2.1
Signal description
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register).
8/52
M25P80
Signal description
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
9/52
SPI modes
M25P80
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Standby mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 3.
Bus Master and memory devices on the SPI bus
VSS VCC R SDO
SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1)
SDI SCK CQD VCC VSS R SPI Memory Device R SPI Memory Device CQD VCC VSS R SPI Memory Device CQD VCC VSS
SPI Bus Master
CS3
CS2 CS1 S W HOLD S W HOLD S W HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure that the M25P80 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 k assuming that the time constant R*Cp (Cp = parasitic , capacitance of the bus line) is shorter than the time during which the Bus Master leaves the SPI bus in high impedance.
10/52
M25P80
SPI modes Example: Cp = 50 pF, that is R*Cp = 5 s <=> the application must ensure that the Bus Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 s. Figure 4.
CPOL CPHA C
SPI modes supported
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
11/52
Operating features
M25P80
4
4.1
Operating features
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Page Program (PP), and Table 15: AC characteristics (75 MHz operation, Grade 6)).
4.2
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
12/52
M25P80
Operating features
4.4
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode. When Chip Select (S) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down mode and Read Electronic Signature (RES) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.
4.5
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 6.4: Read Status Register (RDSR).
4.6
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P80 boasts the following data protection mechanisms:

Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - - - - - Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction).
13/52
Operating features Table 2. Protected area sizes
Memory content
M25P80
Status Register content BP2 BP1 BP0 bit bit bit 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 none Upper sixteenth (Sector 15) Protected area
Unprotected area All sectors(1) (sixteen sectors: 0 to 15) Lower fifteen-sixteenths (fifteen sectors: 0 to 14) Lower seven-eighths (fourteen sectors: 0 to 13) Lower three-quarters (twelve sectors: 0 to 11) Lower half (eight sectors: 0 to 7) none none none
Upper eighth (two sectors: 14 and 15) Upper quarter (four sectors: 12 to 15) Upper half (eight sectors: 8 to 15) All sectors (sixteen sectors: 0 to 15) All sectors (sixteen sectors: 0 to 15) All sectors (sixteen sectors: 0 to 15)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
4.7
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 5). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 5). During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition.
14/52
M25P80 Figure 5. Hold condition activation
Operating features
C
HOLD
Hold Condition (standard use)
Hold Condition (non-standard use)
AI02029D
15/52
Memory organization
M25P80
5
Memory organization
The memory is organized as:

1,048,576 bytes (8 bits each) 16 sectors (512 Kbits, 65536 bytes each) 4096 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 3. Memory organization
Sector 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F0000h E0000h D0000h C0000h B0000h A0000h 90000h 80000h 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h Address range FFFFFh EFFFFh DFFFFh CFFFFh BFFFFh AFFFFh 9FFFFh 8FFFFh 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh
16/52
M25P80 Figure 6.
HOLD W S C D Q Control Logic
Memory organization Block diagram
High Voltage Generator
I/O Shift Register
Address Register and Counter
256 Byte Data Buffer
Status Register
FFFFFh
Y Decoder
Size of the read-only memory area
00000h 256 Bytes (Page Size) X Decoder
000FFh
AI04987
17/52
Instructions
M25P80
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR), Read Identification (RDID) or Release from Deep Powerdown, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.
18/52
M25P80 Table 4.
Instruction WREN WRDI RDID
(1)
Instructions Instruction set
Description Write Enable Write Disable Read Identification Read Status Register Write Status Register Read Data Bytes Read Data Bytes at Higher Speed Page Program Sector Erase Bulk Erase Deep Power-down Release from Deep Powerdown, and Read Electronic Signature Release from Deep Powerdown One-byte instruction code 0000 0110 0000 0100 1001 1111 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1011 1001 06h 04h 9Fh 05h 01h 03h 0Bh 02h D8h C7h B9h Address bytes 0 0 0 0 0 3 3 3 3 0 0 0 1010 1011 ABh 0 0 0 Dummy bytes 0 0 0 0 0 0 1 0 0 0 0 3 Data bytes 0 0 1 to 20 1 to 1 1 to 1 to 1 to 256 0 0 0 1 to
RDSR WRSR READ FAST_READ PP SE BE DP
RES
1. The RDID instruction is available only for parts made with Technology T9HX (0.11m), identified with Process letter '4'. (Details of how to find the Technology Process in the part marking are given in AN1995, see also Section 12: Part numbering.)
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High.
19/52
Instructions Figure 7. Write Enable (WREN) instruction sequence
S 0 C Instruction D High Impedance Q
AI02281E
M25P80
1
2
3
4
5
6
7
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Write Disable (WRDI) instruction sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 8.
1
2
3
4
5
6
7
20/52
M25P80
Instructions
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:

Manufacturer identification (one byte) Device identification (two bytes) A Unique ID code (UID) followed by 16 bytes of CFI data
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (14h). The UID is set to 10h and indicates that 16 bytes, related to the CFI content, are following. Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification, stored in the memory, the 8-bit Unique ID code followed by 16 bytes of CFI content will be shifted out on Serial Data Output (Q). Each bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 5. Read Identification (RDID) data-out sequence
Device identification UID Memory type 20h Memory capacity 14h 10h 16 bytes CFI content
Manufacturer identification 20h
Figure 9.
Read Identification (RDID) instruction sequence and data-out sequence
S 0 C Instruction D Manufacturer Identification High Impedance Q MSB 15 14 13 MSB 3 2 1 0 MSB
AI06809c
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
Device Identification
UID + CFI Data
21/52
Instructions
M25P80
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. Table 6.
b7 SRWD 0 0 BP2 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Block Protect bits Write Enable Latch bit Write In Progress bit
The status and control bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0.
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.
22/52
M25P80
Instructions Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB
AI02031E
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
23/52
Instructions
M25P80
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data input (D). The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. Figure 11. Write Status Register (WRSR) instruction sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
24/52
M25P80 Table 7. Protection modes
Mode Write Protection of the Status Register
Instructions
W SRWD signal bit 1 0 0 0
Memory content Protected area(1) Unprotected area(1)
1
1
Status Register is Writable (if the WREN Software instruction has set the Protected WEL bit) (SPM) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Status Register is Hardware Hardware write protected Protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
0
1
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summarized in Table 7. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.
25/52
Instructions
M25P80
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence
S 0 C Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI03748D
1. Address bits A23 to A20 are Don't Care.
26/52
M25P80
Instructions
6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence
S 0 C Instruction 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31
D High Impedance Q
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte
D
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04006
Q
7 MSB
6
5
4
3
2
1. Address bits A23 to A20 are Don't Care.
27/52
Instructions
M25P80
6.8
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Table 15: AC characteristics (75 MHz operation, Grade 6)). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.
28/52
M25P80 Figure 14. Page Program (PP) instruction sequence
S 0 C Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10
Instructions
28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S
2072 2073 2074 2075 2076 2077 2078
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 Data Byte 3
Data Byte 256
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI04082B
1. Address bits A23 to A20 are Don't Care.
2079
29/52
Instructions
M25P80
6.9
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed. Figure 15. Sector Erase (SE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI03751D
1. Address bits A23 to A20 are Don't Care.
30/52
M25P80
Instructions
6.10
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 16. Bulk Erase (BE) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7
AI03752D
31/52
Instructions
M25P80
6.11
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep Powerdown mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified in Table 14). Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. This releases the device from this mode. The Release from Deep Power-down and Read Electronic Signature (RES) instruction also allows the Electronic Signature of the device to be output on Serial Data Output (Q). The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep Power-down (DP) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tDP
Stand-by Mode
Deep Power-down Mode
AI03753D
32/52
M25P80
Instructions
6.12
Release from Deep Power-down and Read Electronic Signature (RES)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the M25P80 is 13h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for reasons of backward compatibility, only, and should not be used for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered. Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 18. The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S) High after the Electronic Signature has been read at least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the Electronic Signature to be output repeatedly. When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S) must remain High for at least tRES2(max), as specified in Table 15. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 19), still insures that the device is put into Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES1, and Chip Select (S) must remain High for at least tRES1(max), as specified in Table 15. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
33/52
Instructions
M25P80
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence
S 0 C Instruction 3 Dummy Bytes tRES2 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
D High Impedance Q
23 22 21 MSB
3
2
1
0 Electronic Signature Out 7 MSB Deep Power-down Mode Stand-by Mode
AI04047C
6
5
4
3
2
1
0
1. The value of the 8-bit Electronic Signature, for the M25P80, is 13h.
Figure 19. Release from Deep Power-down (RES) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tRES1
High Impedance Q Deep Power-down Mode Stand-by Mode
AI04078B
34/52
M25P80
Power-up and Power-down
7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down
A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the POR threshold value, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level
These values are specified in Table 8. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state:

The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 100 nF). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold value, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)
35/52
Power-up and Power-down Figure 20. Power-up timing
VCC VCC(max) Program, Erase and Write commands are Rejected by the device Chip selection Not Allowed VCC(min) Reset State of the device VWI tPUW tVSL Read Access allowed
M25P80
Device fully accessible
time
AI04009C
Table 8.
Symbol tVSL(1) tPUW(1) VWI(1)
Power-up timing and VWI threshold
Parameter VCC(min) to S low Time delay to Write instruction Write Inhibit voltage Min. 10 1 1 10 2 Max. Unit s ms V
1. These parameters are characterized only.
36/52
M25P80
Initial delivery state
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9
Maximum rating
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 9.
Symbol TSTG TLEAD VIO VCC VESD Storage temperature Lead temperature during soldering Input and output voltage (with respect to ground) Supply voltage Electrostatic discharge voltage (Human Body model)
(2)
Absolute maximum ratings
Parameter Min. -65 Max. 150 see (1) -0.6 -0.6 -2000 VCC + 0.6 4.0 2000 Unit C C V V V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
37/52
DC and AC parameters
M25P80
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10.
Symbol VCC TA
Operating conditions
Parameter Supply voltage grade 3 Ambient operating temperature grade 6 -40 85 C Min. 2.7 -40 Max. 3.6 125 Unit V C
Table 11.
Data retention and endurance
Condition Device grade 6 Min. Max. 100 000 cycles per sector Device grade 3 10 000 20 years at 55 C Unit
Parameter Erase/Program cycles Data Retention
Table 12.
Symbol CL
AC measurement conditions
Parameter Load capacitance Input rise and fall times Input pulse voltages Input timing reference voltages Output timing reference voltages Min. 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC VCC / 2 Max. Unit pF ns V V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 21. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.5VCC 0.3VCC
AI07455
0.2VCC
Table 13.
Symbol COUT CIN
Capacitance(1)
Parameter Output capacitance (Q) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V Min. Max. 8 6 Unit pF pF
1. Sampled only, not 100% tested, at TA = 25 C and a frequency of 20 MHz.
38/52
M25P80 Table 14.
Symbol ILI ILO ICC1
DC and AC parameters DC characteristics
Parameter Input leakage current Output leakage current Grade 6 Standby current Grade 3 Grade 6 Deep Power-down current Grade 3 S = VCC, VIN = VSS or VCC Test condition (in addition to those in Table 10) Min. Max. 2 2 50 A 100 10 S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 75 MHz, Q = open A 100 12 4 15 15 15 15 -0.5 0.7VCC IOL = 1.6 mA IOH = -100 A VCC - 0.2 0.3VCC VCC + 0.4 0.4 mA mA mA mA mA mA V V V V Unit A A
ICC2
ICC3
Operating current (READ) C = 0.1VCC / 0.9.VCC at 20 MHz, Q = open Operating current (PP) Operating current (WRSR) Operating current (SE) Operating current (BE) Input low voltage Input high voltage Output low voltage Output high voltage S = VCC S = VCC S = VCC S = VCC
ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH
39/52
DC and AC parameters Table 15. AC characteristics (75 MHz operation, Grade 6)
M25P80
75 MHz available only for products made in T9HX technology, identified with Process digit "4"(1) Test conditions specified in Table 10 and Table 12 Symbol Alt. Parameter Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR Clock frequency for READ instructions tCLH tCLL Clock High time Clock Low time Clock Rise time(5) (peak to peak) Clock Fall tCSS time(4) (peak to peak) Min. Typ.(2) Max. Unit
fC fR tCH(3) tCL
(3)
fC
D.C. D.C. 11 11 0.1 0.1 5 5 2 5 5 5 100
75 33
MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns
tCLCH(4) tCHCL
(4)
tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ
(4)
S active setup time (relative to C) S not active hold time (relative to C)
tDSU tDH
Data In setup time Data In hold time S active hold time (relative to C) S not active setup time (relative to C)
tCSH tDIS tV tHO
S deselect time Output disable time Clock Low to Output Valid Output hold time HOLD setup time (relative to C) HOLD hold time (relative to C) HOLD setup time (relative to C) HOLD hold time (relative to C)
9 9 0 5 5 5 5 9 9 20 100 3 3 1.8 1.3 15
ns ns ns ns ns ns ns ns ns ns ns s s s ms
tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(4) tHLQZ(4) tWHSL(6) tSHWL
(6)
tLZ tHZ
HOLD to Output Low-Z HOLD to Output High-Z Write Protect setup time Write Protect hold time S High to Deep Power-down mode S High to Standby mode without Electronic Signature Read S High to Standby mode with Electronic Signature Read Write Status Register cycle time
tDP(4) tRES1(4) tRES2(4) tW
40/52
M25P80 Table 15. AC characteristics (75 MHz operation, Grade 6) (continued)
DC and AC parameters
75 MHz available only for products made in T9HX technology, identified with Process digit "4"(1) Test conditions specified in Table 10 and Table 12 Symbol Alt. Parameter Page Program cycle time (256 byte) tPP (7) Page Program cycle time (n bytes, where n = 1 to 4) Page Program cycle time (n bytes, where n = 5 to 256) tSE tBE Sector erase cycle time Bulk erase cycle time Min. Typ.(2) 0.64 0.01 int(n/8) x 0.02(8) 3 20 s s 5 ms Max. Unit
0.6 8
1. Details of how to find the Technology Process in the marking are given in AN1995, see also Section 12: Part numbering. 2. Typical values given for TA = 25C. 3. tCH + tCL must be greater than or equal to 1/ fC 4. Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 7. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) 8. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
41/52
DC and AC parameters Table 16. AC characteristics (25 MHz operation, Grade 3)(1)
Test conditions specified in Table 10 and Table 12 Symbol fC fR tCH tCL
(2)
M25P80
Alt. fC
Parameter Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Clock frequency for READ instructions
Min. D.C. D.C. 18 18 0.1 0.1 10 10 5 5 10 10 100
Typ.
Max. 25 20
Unit MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns
tCLH tCLL
Clock high time Clock low time Clock rise time(4) (peak to peak) Clock fall time(4) (peak to peak)
(2)
tCLCH(3) tCHCL(3) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(3) tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(3) tHLQZ
(3)
tCSS
S active setup time (relative to C) S not active hold time (relative to C)
tDSU tDH
Data in setup time Data in hold time S active hold time (relative to C) S not active setup time (relative to C)
tCSH tDIS tV tHO
S deselect time Output disable time Clock low to output valid Output hold time HOLD setup time (relative to C) HOLD hold time (relative to C) HOLD setup time (relative to C) HOLD hold time (relative to C)
15 15 0 10 10 10 10 15 20 20 100 3 3 1.8 1.5 0.8 int(n/8) x 0.025(7) 5 15
ns ns ns ns ns ns ns ns ns ns ns s s s ms ms
tLZ tHZ
HOLD to Output low-Z HOLD to Output high-Z Write Protect setup time Write Protect hold time S High to Deep Power-down mode S High to Standby mode without Electronic Signature Read S High to Standby mode with Electronic Signature Read Write Status Register cycle time Page Program cycle time (256 bytes) Page Program cycle time (n bytes)
tWHSL(5) tSHWL(5) tDP(3) tRES1(3) tRES2(3) tW(6) tPP(6)
42/52
M25P80 Table 16. AC characteristics (25 MHz operation, Grade 3)(1) (continued)
Test conditions specified in Table 10 and Table 12 Symbol tSE(6) tBE
(6)
DC and AC parameters
Alt.
Parameter Sector Erase cycle time Bulk Erase cycle time
Min.
Typ. 0.8 10
Max. 3 20
Unit s s
1. Preliminary data. 2. tCH + tCL must be greater than or equal to 1/ fC 3. Value guaranteed by characterization, not 100% tested in production. 4. Expressed as a slew-rate. 5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 6. Typical values given for TA = 85 C. 7. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Figure 22. Serial input timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
43/52
DC and AC parameters Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1
M25P80
W tWHSL
tSHWL
S
C
D High Impedance Q
AI07439
Figure 24. Hold timing
S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI02032
44/52
M25P80 Figure 25. Output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D LSB IN
ADDR.
DC and AC parameters
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
45/52
Package mechanical
M25P80
11
Package mechanical
Figure 26. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package outline
A R1 D1 B
MCAB bbb
D
aaa C A
E
E1
E2
e
2x
0.10 C B
aaa C B
b
0.10 C A
A2
D2 L
ddd
A
A1 A3
C
70-ME
1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1.
Table 17.
VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package mechanical data
millimeters inches Max 1.00 0.05 0.0256 0.0079 0.35 0.48 0.0157 0.2362 0.2264 3.20 3.60 0.1339 0.1969 0.1870 3.80 - 0.00 0.50 0.75 12 0.15 0.10 0.05 4.30 - 0.1575 0.0500 0.0039 0.0236 0.1496 - 0.0000 0.0197 0.0295 12 0.0059 0.0039 0.0020 0.1693 - 0.1260 0.1417 0.0138 0.0189 Typ 0.0335 Min 0.0315 0.0000 Max 0.0394 0.0020
Symbol Typ A A1 A2 A3 b D D1 D2 E E1 E2 e R1 L aaa bbb ddd 0.65 0.20 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.10 0.60 0.85 Min 0.80 0.00
46/52
M25P80
Package mechanical Figure 27. SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, package outline
A2 b e D
A c CP
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale. 2. The `1' that appears in the top view of the package shows the position of pin 1.
Table 18.
SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, package mechanical data
millimeters inches Max 2.50 0.00 1.51 0.40 0.20 0.35 0.10 0.25 2.00 0.51 0.35 0.10 6.05 5.02 7.62 1.27 - 0 0.50 8 6.22 8.89 - 10 0.80 0.050 0.198 0.300 - 0 0.020 8 0.016 0.008 0.000 0.059 0.014 0.004 Typ Min Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 - 10 0.031
Symbol Typ A A1 A2 b c CP D E E1 e k L N Min
47/52
Package mechanical
M25P80
Figure 28. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Package is not to scale.
Table 19.
SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data
millimeters inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 - 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 - 0.020 8 0.050 Typ Min Max 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
48/52
M25P80
Part numbering
12
Part numbering
Table 20.
Example: Device type M25P = Serial Flash memory for Code Storage Device function 80 = 8 Mbit (1 Mbit x 8) Operating voltage V = VCC = 2.7 V to 3.6 V Package MW = SO8W (208 mils width) MN = SO8N (150 mils width)(1) MP = VDFPN8 (MLP8) Temperature range 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3(2) = Automotive temperature range, -40 to 125 C. Device tested with High Reliability Certified Flow. Option blank = Standard Packing T = Tape and Reel Packing Plating technology P or G = ECOPACK(R) (RoHs compliant)
1. Package only available for products in the T9HX process. 2. Grade 3 is available only in devices delivered in SO8N packages.
Ordering information scheme
M25P80 - V MW 6 T P
Note:
For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 75 MHz (0.11 m, process digit "4"), please contact your nearest Numonyx Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
49/52
Revision history
M25P80
13
Revision history
Table 21.
Date
Document revision history
Revision Changes Document released as a Product Preview data sheet Clarification of descriptions of entering Standby Power mode from Deep Power-down mode, and of terminating an instruction sequence or data-out sequence. VFQFPN8 package (MLP8) added. Order code (MW) corrected on page 1 for SO8 package. Document promoted to Preliminary Data. Typical Page Program time improved. Write Protect setup and hold times specified, for applications that switch Write Protect to exit the Hardware Protection mode immediately before a WRSR, and to enter the Hardware Protection mode again immediately after. Table of contents, warning about exposed paddle on MLP8, and Pb-free options added. 40MHz AC Characteristics table included as well as 25MHz. Change of naming for VDFPN8 package. Document promoted to full datasheet Improvement to description of reading the 8-bit electronic signature. SO16 package added. SO8W package removed. Soldering temperature information clarified for RoHS compliant devices. Device Grade clarified Automotive range added SO8W package re-instated, but under limited availability Data-retention measurement temperature corrected. Details of how to find the date of marking added. Updated Page Program (PP) instructions in Page Programming, Page Program (PP), Instruction times and Instruction Times (Device Grade 3). SO16 package removed. All packages are ECOPACK(R). MLP8 package renamed as VFQFPN8. Plating technology clarified in Table 20: Ordering information scheme. VFQFPN silhouette modified (see silhouette on page 1). tSHQZ timing modified in Figure 25: Output timing. Device grade 3 specifications removed from datasheet. Data retention conditions changed in Table 11: Data retention and endurance. Figure 3: Bus Master and memory devices on the SPI bus modified and Note 2 added. Note 2 added below Figure 26 and Note 2 added below Figure 27. Note on SO8 package removed below Table 20: Ordering information scheme. SO8N package added (see Figure 28 and Table 19).
24-Apr-2002
1.0
27-Sep-2002
1.1
13-Dec-2002
1.2
24-Oct-2003
2.0
24-Nov-2003 21-Apr-2004 07-May-2004 18-May-2004 05-Aug-2004 01-Aug-2005
2.1 3.0 4.0 5.0 6.0 7.0
20-Oct-2005
8.0
13-Apr-2006
9
20-Jul-2006
10
50/52
M25P80 Table 21.
Date
Revision history Document revision history
Revision Changes Endurance and data retention information added to Features. 50 MHz frequency added, Read Identification (RDID) instruction added, Instruction times table removed, data appended to Table 15: AC characteristics (40 MHz operation, Grade 6) and Table 16. AC characteristics (25MHz operation). Typical tW, tSE and tPP values modified in Table 15: AC characteristics (40 MHz operation, Grade 6) and Note 2 added. VFQFPN8 package specifications updated (see Table 17). Small text changes. Process Technology information added to part numbering (see Table 20). VIO max changed in Table 9: Absolute maximum ratings. Data in Table 15: AC characteristics (75 MHz operation, Grade 6) are preliminary data. tBE typ and fR modified in Table 15. Small text changes. Hardware Write protection added to Features. VCC supply voltage and VSS ground added. Figure 3: Bus Master and memory devices on the SPI bus updated, Note 2 removed and replaced by an explanatory paragraph. Behavior of WIP bit specified at Power-up in Section 7: Power-up and Power-down. TLEAD added to Table 9: Absolute maximum ratings. SO8W and VFQFPN8 package specifications updated (see Section 11: Package mechanical). Note 1 added to Table 20: Ordering information scheme. Temperature grade 3 added (available in products delivered in the SO8N package only). Read Identification instruction modified in Section 6.3: Read Identification (RDID). Inserted UID and CFI content columns in Table 5: Read Identification (RDID) data-out sequence. Modified Data bytes for RDID instruction in Table 4: Instruction set. Modified Q signal in Figure 9: Read Identification (RDID) instruction sequence and data-out sequence. Modified Test condition and maximum value for ICC3 in Table 14: DC characteristics. Table 15: AC characteristics (40 MHz operation, Grade 6) removed. Modified the maximum value for fC in Table 15: AC characteristics (75 MHz operation, Grade 6). Applied Numonyx branding.
22-Sep-2006
11
12-Oct-2006
12
15-Dec-2006
13
09-Jan-2007
14
15-Jun-2007
15
10-Dec-2007
16
51/52
M25P80
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved.
52/52

▲Up To Search▲

Price & Availability of M25P80

	To Download M25P80 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .